The 41st International Symposium on Computer Architecture (ISCA)
http://cag.engr.uconn.edu/isca2014/program.html
Monday, June 16, 2014
Monday, 8:45am-9:45am
Keynote I: Insight into the MICROSOFT XBOX ONE Technology
Chair: Doug Burger, Microsoft
Session 1: Machines and Prototypes
Chair: Mark D. Hill, University of Wisconsin-Madison
Section 2A: Resilience
Chair: Yuan Xie, Pennsylvania State University
Section 2B: Design Space Exploration
Chair: Martha Kim, Columbia University
Section 3A: Caches
Chair: Sandhya Dwarkadas, University of Rochester
Section 3B: GPUs and Parallelism
Chair: Pradeep Dubey, Intel
Tuesday, 8:30am-9:30am
Keynote II: Should Computer Architects Take a Closer Look At Today's Most Pervasive Computer System – The Mobile Phone?
Chair: Steve Keckler, NVIDIA/University of Texas at Austin
Section 4: Emerging Technologies
Chair: Alvin Lebeck, Duke University
Section 5A: NVRAM
Chair: Yoav Etsion, Technion
Section 5B: Datacenters and Cloud
Chair: Doug Carmean, Intel
Section 6A: DRAM
Chair: Fred Chong, University of California at Santa Barbara
Section 6B: Circuits and Architecture
Chair: Carole-Jean Wu, Arizona State University
Wednesday, 8:30am-10:10am
Section 7A: Coherence and Replay
Chair: James Laudon, Google
Section 7B: Security/OOO Processors
Chair: Mohit Tiwari, University of Texas at Austin
Section 8: Accelerators
Chair: Boris Grot, University of Edinburgh
http://cag.engr.uconn.edu/isca2014/program.html
Monday, June 16, 2014
Monday, 8:45am-9:45am
Keynote I: Insight into the MICROSOFT XBOX ONE Technology
Chair: Doug Burger, Microsoft
- Bio: Dr. Ilan Spillinger was instrumental in bringing Kinect for Xbox 360 to market, which continues to proliferate additional innovative programs and products within the Natural User Interface industry. His team's recent efforts include developing the new architecture and silicon design for Xbox One and the new Kinect, which launched in the fall of 2013. Previously, during a six-year tenure with IBM, Dr. Spillinger served as a distinguished engineer and vice president for advanced processor design. In that role he was responsible for development of all Power Architecture-based processors at IBM: server processors, embedded processors, and client-driven solutions. Prior to that, Dr. Spillinger was a principal engineer and manager of the architecture team in Intel Israel, responsible for the definition of x86-based low-cost and low-power microprocessors, specifically the first Intel mobile processor in the Intel Centrino roadmap. Spillinger holds a D.Sc. and M.Sc. in electrical engineering from the Technion Israel Institute of Technology in Haifa, Israel, and joined Microsoft in 2007.
Session 1: Machines and Prototypes
Chair: Mark D. Hill, University of Wisconsin-Madison
- Unifying on-chip and inter-node switching within the Anton 2 network
- A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
- SCORPIO: A 36-Core Research Chip Demonstrating Snoopy Coherence on a Scalable Mesh NoC with In-Network Ordering
Section 2A: Resilience
Chair: Yuan Xie, Pennsylvania State University
- Avoiding Core's DUE & SDC via Acoustic Wave Detectors and Tailored Error Containment and Recovery
- MemGuard: A Low Cost and Energy Efficient Design to Support and Enhance Memory System Reliability
- GangES: Gang Error Simulation for Hardware Resiliency Evaluation
- Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading
Section 2B: Design Space Exploration
Chair: Martha Kim, Columbia University
- ArchRanker: A Ranking Approach to Design Space Exploration
- Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures
- SynFull: Synthetic Traffic Models Capturing Cache Coherent Behaviour
- Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor
Section 3A: Caches
Chair: Sandhya Dwarkadas, University of Rochester
- The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
- SC2: A Statistical Compression Cache Scheme
- The Dirty-Block Index
- Going Vertical in Memory Management: Handling Multiplicity by Multi-policy
Section 3B: GPUs and Parallelism
Chair: Pradeep Dubey, Intel
- Fine-grain Task Aggregation and Coordination on GPUs
- Enabling Preemptive Multiprogramming on GPUs
- Single-Graph Multiple Flows: Energy Efficient Design Alternative for GPGPUs
- HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
Tuesday, 8:30am-9:30am
Keynote II: Should Computer Architects Take a Closer Look At Today's Most Pervasive Computer System – The Mobile Phone?
Chair: Steve Keckler, NVIDIA/University of Texas at Austin
- Bio: Dr. Trevor Mudge received his Ph.D. in Computer Science from the University of Illinois. He is now in the Computer Science and Engineering Department at The University of Michigan, where he served a ten-year term as Director of the Advanced Computer Architecture Laboratory. In 2003 Dr. Mudge was named the Bredt Professor of Computer Engineering. He is the author of numerous papers on computer architecture, programming languages, VLSI design, and computer vision. He has supervised 49 theses in these areas. Dr. Mudge is a Fellow of the IEEE, a member of the ACM, the IET, and the British Computer Society. In addition to his position as a faculty member, he runs Idiot Savants, a chip design consultancy.
Section 4: Emerging Technologies
Chair: Alvin Lebeck, Duke University
- Efficient Digital Neurons for Large Scale Cortical Architectures
- An Examination of the Architecture and System-level Tradeoffs of Employing Steep Slope Devices in 3D CMPs
- STAG: Spintronic-Tape Architecture for GPGPU Cache Hierarchies
Section 5A: NVRAM
Chair: Yoav Etsion, Technion
- Memory Persistency
- Reducing Access Latency of MLC PCMs through Line Striping
- HIOS: A Host Interface I/O Scheduler for Solid State Disks
Section 5B: Datacenters and Cloud
Chair: Doug Carmean, Intel
- Towards Energy Proportionality for Large-Scale Latency-Critical Workloads
- SleepScale: Runtime Joint Speed Scaling and Sleep States Management for Power Efficient Data Centers
- Optimizing Virtual Machine Consolidation Performance on NUMA Server Architecture for Cloud Workloads
Section 6A: DRAM
Chair: Fred Chong, University of California at Santa Barbara
- Row-Buffer Decoupling: A Case for Low-Latency DRAM Microarchitecture
- Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation
- Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
Section 6B: Circuits and Architecture
Chair: Carole-Jean Wu, Arizona State University
- Architecture Implications of Pads as a Scarce Resource
- Increasing Off-Chip Bandwidth in Multi-Core Processors with Switchable Pins
- A Low Power and Reliable Charge Pump Design for Phase Change Memories
Wednesday, 8:30am-10:10am
Section 7A: Coherence and Replay
Chair: James Laudon, Google
- Fractal++: Closing the Performance Gap between Fractal and Conventional Coherence
- OmniOrder: Directory-Based Conflict Serialization of Transactions
- Pacifier: Record and Replay for Relaxed-Consistency Multiprocessors with Distributed Directory Protocol
- Replay Debugging: Leveraging Record and Replay for Program Debugging
Section 7B: Security/OOO Processors
Chair: Mohit Tiwari, University of Texas at Austin
- The CHERI capability model: Revisiting RISC in an age of risk
Section 8: Accelerators
Chair: Boris Grot, University of Edinburgh